The present invention relates generally to semiconductor devices, and more particularly to the layout of input output (IO) buffers associated with semiconductor devices.
Reduction in size of semiconductor devices continues to be an important objective in the design and manufacture of such devices. Generally, semiconductor devices comprise an input output (IO) ring and a logic core as illustrated in FIG. 1. The logic core generally contains combinational and state machine logic to implement specific features of the semiconductor device. The IO ring generally contains signal buffers, and power buffers. Signal buffers include input buffers, output buffers, and bi-directional buffers. Input buffers receive and condition input signals from external to the semiconductor device for use by the logic core. Output buffers receive and condition output signals from the logic core for use external to the semiconductor device. Bi-directional buffers offer the functionality of both input buffers and output buffers. Power buffers provide fixed voltage references and/or supply voltages, such as Vdd and Vss to the semiconductor device.
The minimum number of power buffers needed by a semiconductor device is defined by the number of power buffers needed to prevent a supply voltage related failure from occurring for a specified maximum amount of direct current (DC) needed by the semiconductor device. Generally, supply voltage related failure mechanisms can occur. First, a power buffer can fail when it carries too much current. For example, a power buffer can be physically damaged when it carries too much current. Therefore, by increasing the number of power buffers used, the amount of current through each one can be reduced to assure the power buffers are not physically damaged. A second failure mechanism occurs when the inductance of bond wires prevents enough current from reaching the semiconductor device. During high speed transitions in logic value, output buffer transistors can produce a high current. This high current, in turn, can impress a noise voltage on the low and high power supply buses as a result of a bonding wire, packaging and other inductances that prevent enough current from reaching the semiconductor device. Note that the impressed voltage is given by v=L (di/dt), where v is the noise voltage, L is the inductance of the bonding wire, packaging, etc., and di/dt is the derivative of the current generated by the large driver transistors of the output buffer with respect to time. Thus, the more rapidly that the current of large driver transistors vary in time, the greater the magnitude of the impressed noise signal. This undesirable noise voltage on the high and low power supply buses is commonly referred to as xe2x80x9cground bounce.xe2x80x9d A primary contributor to ground bounce is the bond wire connecting a die to its package. To limit the amount of ground bounce, the number of power buffers for the device are increased, which can result in a significant number of power buffers.
Prior art FIG. 2 illustrates a semiconductor device having a logic core generally square in shape having seven IO devices on each side. Assuming that all the logic core area is used to implement features of the semiconductor device, the logic core device of FIG. 2 is ideally laid out in that the combined width the 7 IO pads is equal to the width of the logic core. If the logic core illustrated in FIG. 2 were smaller, and the same IO were needed, it would not be possible to reduce the overall size of the semiconductor device without changing the width of the IO buffers. The width of the IO buffers can be modified by relaying out each IO buffer. Relaying out buffers is not always a feasible option. Not only is relaying out IO buffers a time consuming process, but there is a practical limit to the extent that the width of IO buffers can be reduced.
FIG. 3 illustrates three adjacent bond pads. The pitch between immediately adjacent bond pads of FIG. 3 have a minimum distance, below which bonding to the pads cannot be properly performed. Therefore, the width of an IO buffer can be limited by the minimum pitch which must be maintained. In addition, FIG. 3 illustrates that each IO buffer includes a bond pad area and an active buffer area, such that the bond pad areas form a bond pad ring within the IO ring illustrated in FIG. 1.
Therefore, a method and/or apparatus capable of reducing the overall area utilized by the IO ring portion of a semiconductor device would be useful.